ZFSA2: A power aware X - bit filling approach for VLSI circuits

Optimization Techniques for Low Power VLSI Circuits

Power dissipation has emerged as an important design parameter in the design of microelectronic circuits, especially in portable computing and personal communication applications. In this paper, we survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are considered.

Power Minimisation Techniques for Testing Low Power VLSI Circuits

POWER AND TIMING MODELLING, OPTIMISATION AND SIMULATION Leakage current aware high-level estimation for VLSI circuits

The ever-growing leakage current of MOSFETs in nanometre technologies is the major concern to high performance and power efficient designs. Dynamic power management via powergating is effective to reduce leakage power, but it introduces power-up current that affects the circuit reliability. The authors present an in-depth study on high-level modelling of power-up current and leakage current in ...

A Fundamental Basis for Power-Reduction in VLSI Circuits

Presented in this paper is a fundamental mathematical basis for power-reduction in VLSI systems. This basis is employed to 1.) derive lower bounds on the power dissipation in digital systems and 2.) unify existing power-reduction techniques under a common framework. The proposed basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed...

Power Simulation and Estimation in VLSI Circuits

In the past the major concerns of the VLSI designer were area speed and cost power consideration was typically of secondary importance In recent years how ever this has begun to change and increasingly power is being given comparable weight to other design considerations Several factors have contributed to this trend including the remarkable success and growth of the class of battery powered pe...